The MACHOP language is used to define the instruction set of the target processor that may be used to translate the PSEUDO machine code into the target machine code. The function of a MACHOP is to define the binary output to the object file and format of a pseudo assembly-listing file. The MACHOP operates in a bit addressable memory space allowing any size of addressable unit(8 bits 16 bits 24 bits 36 bits etc). In fact different sizes could be mixed, Some processors have different size data and instruction storage. A MACHOP outputs bit fields. These fields may be combined for display in a pseudo assembly listing.

MACHOP syntax defination

The following MACHOP defines the output for the IPX86 family processor MOV instruction:

.MACHOP	MOV dest[ixd],source[ixs] -


 .MORG 8: H(16): $/8;
  if isnumber(source) then {
    if isreg(dest) then {
      +H(4):0b1011;
        (1); if size:(dest) = 8 then 0 else 1;
        (3): dest;}
    else {
      if !frame:(dest) and segment:(dest) != curSegment then
        +H(8): overide(dest)

        +H(7):0b1100011;
          (1): if size:(dest) = 8 then 0 else 1;
        +H(2): mod(dest);
          (3): 0;
          (3): R_M(dest);
        +H(szoff): offset:(dest/8);}
    +H(size:(dest)):  source}


  else if isreg(source) && isreg(dest) then {
    +H(7):0b1000100;
      (1): if size:(dest) = 8 then 0 else 1;
    +H(2):0b11;
      (3):source;
      (3):dest;}
  else if isreg(source) then {
    +H(7):0b1000100;
      (1): if size:(dest) = 8 then 0 else 1;
    +H(2): mod(dest);
      (3):source;
      (3):R_M(dest);}
  else  isreg(dest) then {
    +H(7):0b1000101;
      (1): if size:(source) = 8 then 0 else 1;
    +H(2): mod(source);
      (3):source;
      (3):R_M(source);}
  else if issegreg(dest) then {
    +H(8):0b10001110;
      (2): mod(source);
      (3): issegreg(dest);
      (3): R_M(source);
    if !isreg(source);
      +H(szoff): offset:(source/8);}
  else {
    +H(8):0b10001100;
      (2): mod(dest);
      (3): issegreg(source);
      (3): R_M(dest);
    if !isreg(source);
      +H(szoff): offset:(dest/8);}

The following uses the vectored opcode form to define many opcodes with one MACHOP. In the following #OP contains the value associated with the vectored entry definitions following the body of the MACHOP. The following defines the output for parameterless single byte instructions of the IPX86 family of processors

.MACHOP	#OP -


 .MORG 8: H(16): $/8;


  +H(8): OP;


  #AAA     0b00110111;
  #AAS     0b00111111;
  #CBW     0b10011000;
  #CLC     0b11111000;
  #CLD     0b11111100;
  #CLI     0b11111010;
  #CMC     0b11110101;
  #CWD     0b10011001;
  #DAA     0b00100111;
  #DAS     0b00101111;
  #HLT     0b11110100;
  #INT3    0b11001100;
  #INTO    0b11001110;
  #IRET    0b11001111
  #LAHF    0b10011111;
  #LEAVE   0b11001001;
  #NOP     0b10010000;
  #POPA	   0b01100001;
  #POPF    0b10011101;
  #PUSHA   0b01100000;
  #PUSHF   0b10011100;
  #SAHF    0b10011110;
  #STC     0b11111001;
  #STD     0b11111101;
  #STI     0b11111011;
  #XLAT    0b11010111;